When integrated circuits are manufactured, certain quality control tests are performed on the integrated circuit (IC) chip to ensure that only those chips that are within acceptable margins of functionality are shipped to the consumer. For example, memory tests can be performed on the integrated circuit chip to test for defects in the integrated chip. According to certain approaches, if a given IC chip fails the previously mentioned memory tests, then such an IC chip is marked for rejection and is not shipped to the customer. Other examples of tests are those that test the proper functioning of arithmetic logic units (ALUs) in application specific integrated circuits (ASICs). When one or more ALUs in the IC chip fail specific function tests then the entire IC chip is rejected. Thus, such approaches to quality control testing result in waste and relatively low manufacturing yields. Further, when the tests are performed, an external controller that is independent of integrated circuit's ALUs has to decide which ALUs to remove or disable. Thus, the chip manufacturer either needs to coordinate with the customer's control system for testing of the ASICs or at the very least, the manufacturer needs to design and/or make a separate external controller that is capable of deciding which ALUs to disable in response to the testing results.
In view of the foregoing, a more efficient method is needed to increase the manufacturing yield of functional ASICs in a manner that is transparent to an external controller used in the testing of the ASICs.